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 Sun Microsystems SuperSPARC TMX390Z50GF-40
Sun Microsystems SuperSPARC TMX390Z52GF STP1020APGA-60
Sun Microsystems microSPARC II STP 1012, 70 MHz
Sun Microsystems microSPARC II STP 1012A, 85 MHz
Sun Microsystems microSPARC II STP 1012, 110 MHz
Sun Microsystems SuperSPARC II STP 1021APGA, 85 MHz
Sun Microsystems UltraSPARC STP 1030, 143 MHz
Sun Microsystems UltraSPARC STP 1030, 200 MHz
Sun Microsystems UltraSPARC II STP 1031, 250 MHz
Sun Microsystems UltraSPARC II STP 1031, 250 MHz (w/ Bolts)
Sun Microsystems UltraSPARC II STP 1031, 300 MHz
Sun Microsystems UltraSPARC II STP 1031, 336 MHz
Sun Microsystems UltraSPARC II STP 1032, 400 MHz
Sun Microsystems UltraSPARC II STP 1032A, 400 MHz
Sun Microsystems UltraSPARC II STP 1032A, 450 MHz
Sun Microsystems UltraSPARC IIi SME 1040, 333 MHz
Sun Microsystems UltraSPARC IIi SME 1430, 360 MHz
Sun Microsystems UltraSPARC IIi SME 1430, 440 MHz
Sun Microsystems UltraSPARC IIe SME 1701, 400 MHz
Sun Microsystems UltraSPARC IIe SME 1701, 500 MHz
Sun Microsystems UltraSPARC III SME 1052A
Sun Microsystems UltraSPARC III SME 1052B, 900 MHz
Sun Microsystems UltraSPARC III SME 1052B, 1015 MHz
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» Sun Microsystems overview
» all SPARC chips
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The Sun SuperSPARC Processor
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The Texas Instruments made Sun SuperSPARC CPU, introduced in 1992, is a SPARC V8 (32-bit) compliant RISC CPU that was used for Sun's SPARCstation 20/xx workstations and some servers during early to mid-1990s. It has an on-chip 20k 5-way set-associative instruction cache (which is very uncommon) plus an on-chip 16k 4-way set-associative data cache and runs at up to 60MHz.
The SuperSPARC was intended for use in a broad range of applications from uniprocessor desktop machines to large multiprocessor servers, built with the SuperSPARC processor either in direct MBus mode or in VBus mode with the use of an external cache controller. An external cache controller supports multiprocessor configurations using either MBus or XBus interfaces with up to 2 MB of secondary cache.
The SuperSPARC was the first CPU to feature superscaling, or the ability to process multiple instructions in a single clock cycle via multiple execution units.
For rendering Pixar's "Toy Story", the first full length movie to be created only by computers, Pixar used more than 100 Sun SPARCstation 20 workstations and a SPARCserver 1000 to render the whole film. They all had TMS390 SuperSPARC processors.
References:
SuperSPARC Data Sheet |
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The Sun Microsystems microSPARC II Processor
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The microSPARC II, introduced in 1994, is a highly integrated microprocessor, implementing the SPARC V8 specification. It includes a variety of chipset logic functions on the chip like a programmable DRAM controller, graphics interface support, internal and boundary scan through JTAG interface, power management and clock generation capabilities. It was targeted for low-cost uniprocessor applications operating at low voltage for optimized power consumption.
The microSPARC II was used in Sun SPARCstation 4, 5 and Voyager workstations and the JavaStation thin client. |
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The Sun Microsystems SuperSPARC II Processor
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| The SuperSPARC II, introduced in 1994, is an enhanced version of the SuperSPARC CPU. It maintains the foundation of the SuperSPARC architecture and incorporates a number of improvements. A second-level external cache controller, optional with the original SuperSPARC, is required with the SuperSPARC II design. The SuperSPARC II additionally supports dual-byte ordering as specified in the SPARC V9 architecture (thus being still 32-bit SPARC V8 compliant). Improvements include a streamlined integer pipeline, a redesigned FPU to offer better superscalar performance and a memory management unit with a TLB (translation lookaside buffer) for each of the on-chip caches. |
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The Sun UltraSPARC Processor
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The UltraSPARC, introduced in late 1994 and available in 1995, was Sun's first general-purpose processor to deliver SPARC V9 compliant 64-bit compute power with advanced graphics throughput and real-time video performance. Along with 64-bit data and addressing, the UltraSPARC had the potential to execute as many as four RISC instructions per clock cycle and featured a built-in graphics processing unit. It also added a special set of VIS (Visual Instruction Set) instructions for accelerating media and graphics applications. The UltraSPARC supports 2D as well as 3D graphics, image processing, real-time video compression and decompression with no additional hardware support. Many of these optimized graphics instructions execute complex graphics operations in a single clock cycle.
The 64-bit core of the first UltraSPARC is essentially the same as that of all subsequent
UltraSPARC chips. UltraSPARC II (shipped in 1997) provided better multiprocessing
support and the UltraSPARC III (shipped in 2001) integrated more cache memory,
but performance improvements have largely derived from clock speed increases.
References:
SPARC at Wikipedia
UltraSPARC introduction
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The Sun UltraSPARC II Processor
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The UltraSPARC II, introduced in 1997, was Sun's second generation high-performance, highly integrated superscalar processor implementing the SPARC V9 64-bit architecture. Building on the UltraSPARC I pipeline, UltraSPARC II scaled up its computation, multimedia, and networking performance. The design was retargeted for 0.35 µ (later 0.25 µ) CMOS, 5-layer metal technology, and added functional enhancements to boost data bandwidth, reduce cache-miss penalties, and improve floating-point and multimedia (VIS) performance. It also added multiple SRAM modes and variable system bus to processor clock ratios.
References:
SPARC at Wikipedia
UltraSPARC II announcement
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The Sun Microsystems UltraSPARC IIi Processor
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Introduced in 1997, the UltraSPARC IIi, a highly integrated UltraSPARC II with PCI interface, was developed to meet the needs of embedded 64-bit computing and low-end workstation systems. It delivered quite high computing throughput in a highly integrated package, with efficient power consumption to enable compact, low-cost system designs. System design was eased with all high speed interconnects integrated into the IIi. System designers were thus able to use the performance of the UltraSPARC II with PC-class, PCI-based mother boards and components.
The UltraSPARC IIi processor was introduced as a low-end entry to UltraSPARC performance and scalability, targeted for datacom, Internet, telecom, and network environments.
References:
UltraSPARC IIi User's Manual |
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The Sun UltraSPARC IIe Processor
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The UltraSPARC IIe, introduced in 2000, is an embedded version of the UltraSPARC II, targeting rack-mounted servers, line cards, telecommunications switches and network routers.
This integrated processor incorporates an execution unit based on Sun's SPARC V9 64-bit architecture that incorporates a floating-point unit and VIS multimedia extensions, a unified, four-way-set-associative, 256-kbyte integrated L2 cache, a 32-bit, 66-MHz PCI-bus controller and a PC-100 SDRAM controller with ECC, eliminating the need for an external "Northbridge" chip. It is packaged in a low-cost, 370-pin ceramic PGA.
References:
UltraSPARC IIe at Sun |
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The Sun UltraSPARC III Processor
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The UltraSPARC III, initially shipped in 2001, is the third generation from the UltraSPARC family. It features Scalable Shared Memory (SSM) and is able to scale to up to 1000 processors in a single system.
It was one of the most complex processors available then, comprising 29 million transistors and features such as an embedded memory controller and 9.6 GB-per-second address bus for massive scalability, support for a large 8 MB ECC-protected external cache for minimal latency and a new error isolation and correction "Uptime Bus" (a bus that runs independent of the main system bus, allowing the CPU to be powered-on, configured and tested without requiring that the majority of the system be operational) for high system reliability.
The UltraSPARC III was Sun's first move to boost its aging chip architecture after almost five years. The chip was due 18 months before its introduction, but was delayed for reasons never explained.
The initial version of UltraSPARC III was fabricated by Texas Instruments in a 0.18 µ process technology with aluminum (Al) metal layers. Implemented in this technology, UltraSPARC III operates at frequencies of 600 MHz and 750 MHz. In 2001, UltraSPARC III was upgraded to take advantage of a new TI process technology featuring 0.15 µ features with Copper (Cu) metal layers. Implemented in this more advanced generation of technology, UltraSPARC III operates at frequencies of 900 and 1050 MHz. In 2002, UltraSPARC III Cu was upgraded again to TI’s latest 0.13 µ generation of technology, reaching a top operating frequency of 1200 MHz.
References:
UltraSPARC III announcement
UltraSPARC III at Sun
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