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Fujitsu SPARC MB86900 |
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| Donated by Sunopsis, the Sun Museum. Thanks a lot! |
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| Core Frequency: | 15 MHz | | Board Frequency: | 15 MHz |
| Data bus (ext.): | 32 Bit | | Address bus: | 32 Bit | | Transistors: | 110,000 | | Circuit Size: | 1.30 µ | | Voltage: | 5 V | | Introduced: | 1986 | | Manufactured: | week 46/1987 | | Made in: | Japan | | Package Type: | Ceramic
PGA-256 |
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Fujitsu SPARC MB86902 |
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| Core Frequency: | 25 MHz | | Board Frequency: | 25 MHz |
| Data bus (ext.): | 32 Bit | | Address bus: | 32 Bit | | Introduced: | 1986 | | Manufactured: | week 04/1991 | | Made in: | Japan | | Package Type: | Plastic
PQFP-160 |
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The HAL SPARC64-III or SPARC64-GP is a SPARC processor conforming to the 64-bit SPARC V9 architecture. When it was released in 1998 it delivered better overall performance than Sun's competing UltraSPARC II at comparable and even lower clock speeds. It has an out-of-order execution engine that can process 63 instructions at once, more than twice the number of instructions possible with the UltraSPARC processor's in-order core. It also has two floating point and two load-store units, delivering twice as many floating point results per cycle as UltraSPARC II. In addition, its instruction and data caches are four times larger and use a four-way set-associative organization, incurring lower miss rates than the caches in UltraSPARC II. Furthermore, the SPARC64-III uses separate buses for the L2 cache and system interfaces, providing greater sustainable memory bandwidth than the UltraSPARC II at comparable clock speeds. In addition, the SPARC64-III uses ECC or parity in TLB and cache arrays, making them more reliable and suitable in mission critical applications than the UltraSPARC II chips, which do not.
References:
SPARC64-III User's Guide
SPARC64-III Microprocessor Report |
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The first two implementations of the SPARC architecture, Fujitsu MB86900 and Cypress/ROSS CY7C601, were designed using high-speed CMOS technology with processor clock speed in the range of 16.6 to 33 MHz. In a system with a reasonable size external cache, these processors execute integer operations at a rate of approximately 1.5 clock cycles per instruction, resulting in a sustained performance in the range of 10 to 20 MIPS. The MB86900 design uses a single 20,000-gate 1.3 µ CMOS gate array and operates at a cycle time of 60 ns. The CY7C601 is a full custom chip designed using a 0.8 µ CMOS process and operates at a cycle time of 30 ns.