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The Cypress / ROSS Technology CY7C601 Processor
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The Cypress CY7C601 is the 2nd generation SPARC processor, developed by ROSS Technology, then a subsidary of Cypress Semiconductor. When Cypress sold ROSS to Fujitsu in 1993 the chip was renamed to ROSS RT601.
The CY7C601 has no on-chip cache; off-chip cache is 64K, write-back (can be run in write-through mode, but the OS puts it in write-back mode), direct-mapped, virtually-indexed and virtually and physically tagged (for MP cache coherency). Lines are 32 bytes.
The first two implementations of the SPARC architecture, Fujitsu MB86900 and Cypress/ROSS CY7C601, were designed using high-speed CMOS technology with processor clock speed in the range of 16.6 to 33 MHz. In a system with a reasonable size external cache, these processors execute integer operations at a rate of approximately 1.5 clock cycles per instruction, resulting in a sustained performance in the range of 10 to 20 MIPS. The MB86900 design uses a single 20,000-gate 1.3 µ CMOS gate array and operates at a cycle time of 60 ns. The CY7C601 is a full custom chip designed using a 0.8 µ CMOS process and operates at a cycle time of 30 ns. |
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