engineering sample samples qualification cpu processor prozessor information mhz pictures core frequency chip packaging info ic x86 museum collection amd cyrix harris ibm idt iit intel motorola nec sgs sgs-thomson siemens ST signetics mhs ti texas instruments ulsi hp umc weitek zilog 4004 4040 8008 808x 8085 8088 8086 80188 80186 80286 286 80386 386 i386 Am386 386sx 386dx 486 i486 586 486sx 486dx overdrive 80187 80287 387 487 pentium 586 5x86 386dlc 386slc 486dx2 mmx ppro pentium-pro pro athlon duron z80 sparc alpha dec dirk oppelt
Clipper class ICs
Clipper information
The Clipper architecture was originally developed at Fairchild Semiconductor in Oct. 1985, and began shipping in 1986. The architecture was acquired by Intergraph Corporation in 1987. Intergraph was a manufacturer of high-end graphics workstations.

The Clipper architecture is available in a family of implementations, ranging from CMOS to ECL implementations. First and second generation parts included the C100 and C300. The C300 had improved floating point, higher clock speeds, and was superpipelined. The C400, a third generation part, was introduced in September 1990. In 1993, Intergraph dropped the planned 1994 introduction of the next-generation C5 project, an 8 pipeline affair, in favor of a relationship with Sparc, and Windows NT.

The latest implementation of the Clipper architecture is the superscalar, superpipelined C400 or C4. It is able to issue two instructions per clock, and has a four stage pipeline. Full 64 bit data paths are used between functional units.
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3 Clipper chips in collection: show thumbnails
  Clipper C100
   Clipper C100
  Clipper C4
   Clipper C4
  Clipper FPU
   Clipper C4 FPU