|November 2006 updates and changes
9 additions to the collection today:
DEC Alpha Processors
The DEC Alpha, also known as the Alpha AXP, is a 64-bit RISC microprocessor originally developed and fabricated by Digital Equipment Corp (DEC). Designed to power successors to the VAX line of computers, it was used in a variety of DEC workstations and servers, eventually forming the basis for almost all of their entire mid-to-upper-scale lineup. Several third-party vendors also produced Alpha systems, as well as PC compatible form factor motherboards.
Alpha supported both the VMS operating system, as well as Digital UNIX. Later open source operating systems also ran on the Alpha, notably Linux and BSD UNIX flavors. Microsoft supported the processor in Windows NT until NT 4.0 SP6 but did not extend Alpha support beyond release candidate 2 of Windows 2000.
The Alpha series was sold, along with DEC as a whole, to Compaq in 1998. Compaq, already an Intel customer, decided to phase out Alpha in favor of the forthcoming Intel Itanium architecture, and sold all Alpha intellectual property to Intel in 2001, effectively "killing" the product. Hewlett-Packard purchased Compaq later that same year, continuing development of the existing product line until 2004, and promising to continue selling Alpha-based systems, largely to the existing customer base, until 2006.
Alpha at Wikipedia
DEC Documentation Library
DEC Documentation Archives
HP Alpha Systems
Alpha: The History in Facts and Comments
Brief Introduction to Alpha
Alpha 21064 (EV4)
The first processors of the Alpha family were designated the DECchip 21064 series (the "21" signifying the 21st century, "0" corresponding to the processor generation and the "64" indicating 64 bits), also code-named EV4. Internally, Alpha processors were also identified by EV numbers, EV officially standing for "Extended VAX".
|Alpha EV4 and EV45 product codes
|21064A-PC (for NT)
The first few generations of the Alpha chips were some of the most innovative CPUs of their time. The EV4 was the first CMOS microprocessor whose operating frequency rivalled higher-powered minicomputers and mainframes.
The EV4 core is a dual-issue (it can issue 2 instructions per CPU clock) superpipelined core with integer unit, floating point unit and branch prediction. It is fully bypassed and has 64-bit internal data paths and tightly coupled 8 KB caches, one each for Instruction and Data. The caches are write-through.
6 new Alpha 21064 in the collection:
DEC Alpha AXP 21-35023-13 (21064-AA, 150 MHz)
The first Alpha workstation was available in November 1992: The DEC 3000 Model 500 AXP (code-named Flamingo), with a 150 MHz EV4, 512 KB of L2-cache, 32 MB RAM, integrated 8-bit video controller with 2 MB VRAM, 1 GB SCSI HDD, SCSI CD-ROM, built-in 10 Mbit Ethernet controller (thick coaxial and twisted pair), built-in sound and ISDN controllers, equipped with a 19" monitor (1280x1024 at 72Hz). The price was quite impressive: 39000 US$.
Design of the DEC 3000
DEC Alpha AXP 21-35023-21 (21064, 190 MHz)
A 190 MHz 21064 mounted on a DEC B2020-AA CPU board (50-23143-03) for the DEC AlphaStation 2000. Later revisions of the B2020-AA (54-23144-03) are 200 MHz versions for the AlphaStation 2100 4/200.
DEC Alpha AXP 21-35023-21 (21064, 200 MHz)
DEC Alpha AXP 21-35023-12 (21064, 200 MHz)
DEC Alpha AXP 21-40532-08 (21064-P1, 275 MHz)
The P1-version of the 21064A is designed for Windows NT desktop PCs and workstations. This CPU is from my DEC Alpha XL266, a machine shipped with Windows NT 4.
DEC Alpha AXP 21-40532-06 (21064-EB, 300 MHz)
Alpha 21164 (EV5)
The Alpha 21164 or EV5 became available in 1995 at processor frequencies of up to 333 MHz. In July 1996 the line was speed bumped to 500 MHz, in March 1998 to 600 MHz. DEC unveiled the first information about the 2nd generation Alpha processor at the Hot Chips conference in Palo Alto on August 14th 1994. The official release of the 21164 (EV5) was on September 7th 1994. The processor was based on the core of the EV45 and was more an evolution than a revolutionary new design.
|Alpha EV5, EV56 and PCA56 product codes
|21164 (for NT)
|21164 (for NT)
|21164A (for NT)
The EV5 core is a quad-issue core. It also has a tightly-coupled 96 KB on-chip second-level cache (the SCache) which is 3-way set associative and write-back (in contrast to the L1 caches). The EV4 to EV5 performance increase is better than just the increase achieved by clock speed improvements. As well as the bigger caches and quad issue, there are microarchitectural improvements to reduce producer/consumer latencies in some paths.
3 new Alpha 21164 in the collection:
DEC Alpha AXP 21-40658-17 (21164-BA, 300 MHz)
DEC Alpha AXP 21-43918-45 (21164-P8, 533 MHz)
The P8-version of the 21164 Alpha processor is designed for Windows NT desktop PCs and workstations.
DEC Alpha AXP 211PC-03 (21164PC, 533 MHz)
The Alpha 21164PC is much like the Alpha 21164, with no L2 cache on board, and an additional 8K of instruction cache to keep costs down, and performance adequate. It was created to be a volume processor for workstations, but never really sold in any great numbers due to the weak L1 cache.
References: Byte.com: Alpha Arrives at the Desktop Alpha 21164PC announcement
|May - October 2006 updates and changes
|...::: cpu-collection.de now has more than 900 different chips online :::...
24 additions to the collection today:
| (Scalable Processor ARChitecture) is an open set of technical
specifications that any person or company can license and use to
develop microprocessors and other semiconductor devices based on
| published industry standards.
| SPARC was invented in the labs of Sun Microsystems Inc., based upon pioneering
| research into Reduced Instruction Set Computing (RISC) at the University of California
| at Berkeley. The first standard product based on the SPARC architecture, the MB86900,
|was produced by Sun and Fujitsu in 1986; Sun followed in 1987 with its first workstation based on a SPARC processor.
In 1989, Sun Microsystems transferred ownership of the SPARC specifications to an independent, non-profit organization, SPARC International, which administers and licenses the technology and provides compliance testing and other services for its members.
As an open architecture, the SPARC specifications have been refreshed with advanced technologies, evolving to SPARC Version 9. All versions of the architecture are available today.
24 new SPARC processors and coprocessors in the collection:
Cypress / ROSS Technology SPARC CY7C601
The Cypress CY7C601 is the 2nd generation SPARC processor, developed by ROSS Technology, then a subsidary of Cypress Semiconductor. When Cypress sold ROSS to Fujitsu in 1993 the chip was renamed to ROSS RT601.
The CY7C601 has no on-chip cache; off-chip cache is 64K, write-back (can be run in write-through mode, but the OS puts it in write-back mode), direct-mapped, virtually-indexed and virtually and physically tagged (for MP cache coherency). Lines are 32 bytes.
The first two implementations of the SPARC architecture, Fujitsu MB86900 and Cypress/ROSS CY7C601, were designed using high-speed CMOS technology with processor clock speed in the range of 16.6 to 33 MHz. In a system with a reasonable size external cache, these processors execute integer operations at a rate of approximately 1.5 clock cycles per instruction, resulting in a sustained performance in the range of 10 to 20 MIPS. The MB86900 design uses a single 20,000-gate 1.3 µ CMOS gate array and operates at a cycle time of 60 ns. The CY7C601 is a full custom chip designed using a 0.8 µ CMOS process and operates at a cycle time of 30 ns.
It was used in Sun SPARCstation and SPARCserver 330, 370 and 390, the 40 MHz version is from a SPARCstation 2.
Cypress CY7C601-40GC (40 MHz PGA version)
Cypress CY7C601-40 (40 MHz QFP version) on a ROSS Technology MBus module together with
Cypress CY7C602-40 SPARC FPU
The very first SPARC MBus module Ross CYM6001K (Sun part no. 501-1301) for the SPARCstation 2.
The module has mounted a CY7C604 MMU, the CY7C601 CPU and a CY7C602 FPU chip.
LSI Logic SPARC S1C0010 100-2921-01
A SPARC IU (Integer Unit) from my SPARCstation IPC 'Phoenix'. SPARC V7 architecture.
Weitek 3170 025-GCD
A 25 MHz Weitek SPARC FPU for the SPARCstation 1+ 'Campus B' (4/65). The 3170 was used for a short time only and later replaced by a Weitek 3172.
Fujitsu SPARClite MB86831
The SPARClite family is a series of RISC processors with a workstation 32-bit SPARC architecture optimized for embedded applications. Due to its high performance, the SPARClite family is used mainly in image processors such as digital still cameras and laser beam printers.
Sun Microsystems SuperSPARC
The Texas Instruments made Sun SuperSPARC CPU, introduced in 1992, is a SPARC V8 (32-bit) compliant RISC CPU that was used for Sun's SPARCstation 20/xx workstations and some servers during early to mid-1990s. It has an on-chip 20k 5-way set-associative instruction cache (which is very uncommon) plus an on-chip 16k 4-way set-associative data cache and runs at up to 60MHz.
The SuperSPARC was intended for use in a broad range of applications from uniprocessor desktop machines to large multiprocessor servers, built with the SuperSPARC processor either in direct MBus mode or in VBus mode with the use of an external cache controller. An external cache controller supports multiprocessor configurations using either MBus or XBus interfaces with up to 2 MB of secondary cache.
The SuperSPARC was the first CPU to feature superscaling, or the ability to process multiple instructions in a single clock cycle via multiple execution units.
For rendering Pixar's "Toy Story", the first full length movie to be created only by computers, Pixar used more than 100 Sun SPARCstation 20 workstations and a SPARCserver 1000 to render the whole film. They all had TMS390 SuperSPARC processors.
SuperSPARC Data Sheet
Sun Microsystems SuperSPARC TMX390Z52GF STP1020APGA-60
A 60 MHz SuperSPARC processor
Sun Microsystems microSPARC II
The microSPARC II, introduced in 1994, is a highly integrated microprocessor, implementing the SPARC V8 specification. It includes a variety of chipset logic functions on the chip like a programmable DRAM controller, graphics interface support, internal and boundary scan through JTAG interface, power management and clock generation capabilities. It was targeted for low-cost uniprocessor applications operating at low voltage for optimized power consumption.
The microSPARC II was used in Sun SPARCstation 4 and 5 and Voyager workstations and the JavaStation thin client.
Sun Microsystems SuperSPARC II
The SuperSPARC-II, introduced in 1994, is an enhanced version of the SuperSPARC CPU. It maintains the foundation of the SuperSPARC architecture and incorporates a number of improvements. A second-level external cache controller, optional with the original SuperSPARC, is required with the SuperSPARC II design. The SuperSPARC II additionally supports dual-byte ordering as specified in the SPARC V9 architecture (thus being still 32-bit SPARC V8 compliant). Improvements include a streamlined integer pipeline, a redesigned FPU to offer better superscalar performance and a memory management unit with a TLB (translation lookaside buffer) for each of the on-chip caches.
SuperSPARC II STP 1021APGA, 85 MHz
A 85 MHz SuperSPARC II on an SM81 MBus module (Sun part no. 501-2953)
Sun Microsystems UltraSPARC
The UltraSPARC, introduced in late 1994 and available in 1995, was Sun's first general-purpose processor to deliver SPARC V9 compliant 64-bit compute power with advanced graphics throughput and real-time video performance. Along with 64-bit data and addressing, the UltraSPARC had the potential to execute as many as four RISC instructions per clock cycle and featured a built-in graphics processing unit. It also added a special set of VIS (Visual Instruction Set) instructions for accelerating media and graphics applications. The UltraSPARC supports 2D as well as 3D graphics, image processing, real-time video compression and decompression with no additional hardware support. Many of these optimized graphics instructions execute complex graphics operations in a single clock cycle.
The 64-bit core of the first UltraSPARC is essentially the same as that of all subsequent UltraSPARC chips. UltraSPARC II (shipped in 1997) provided better multiprocessing support and the UltraSPARC III (shipped in 2001) integrated more cache memory, but performance improvements have largely derived from clock speed increases.
SPARC at Wikipedia
UltraSPARC STP 1030, 143 MHz
A 143 MHz UltraSPARC
Sun Microsystems UltraSPARC II
The UltraSPARC II, introduced in 1997, was Sun's second generation high-performance, highly integrated superscalar processor implementing the SPARC V9 64-bit architecture. Building on the UltraSPARC I pipeline, UltraSPARC II scaled up its computation, multimedia, and networking performance. The design was retargeted for 0.35 µ (later 0.25 µ) CMOS, 5-layer metal technology, and added functional enhancements to boost data bandwidth, reduce cache-miss penalties, and improve floating-point and multimedia (VIS) performance. It also added multiple SRAM modes and variable system bus to processor clock ratios.
UltraSPARC II announcement
UltraSPARC II STP 1031, 250 MHz (w/ Bolts)
This version of the UltraSPARC II has bolts to fix a cooler.
UltraSPARC II STP 1031, 250 MHz
UltraSPARC II STP 1032, 400 MHz
UltraSPARC II STP 1032A, 400 MHz
UltraSPARC II STP 1032A, 450 MHz
Sun Microsystems UltraSPARC IIi
Introduced in 1997, the UltraSPARC IIi, a highly integrated UltraSPARC II with PCI interface, was developed to meet the needs of embedded 64-bit computing and low-end workstation systems. It delivered quite high computing throughput in a highly integrated package, with efficient power consumption to enable compact, low-cost system designs. System design was eased with all high speed interconnects integrated into the IIi. System designers were thus able to use the performance of the UltraSPARC II with PC-class, PCI-based mother boards and components.
The UltraSPARC IIi processor was introduced as a low-end entry to UltraSPARC performance and scalability, targeted for datacom, Internet, telecom, and network environments.
UltraSPARC IIi User's Manual
UltraSPARC IIi SME 1040, 333 MHz
UltraSPARC IIi SME 1430, 360 MHz
UltraSPARC IIi SME 1430, 440 MHz
Sun Microsystems UltraSPARC IIe
The UltraSPARC IIe, introduced in 2000, is an embedded version of the UltraSPARC II, targeting rack-mounted servers, line cards, telecommunications switches and network routers.
This integrated processor incorporates an execution unit based on Sun's SPARC V9 64-bit architecture that incorporates a floating-point unit and VIS multimedia extensions, a unified, four-way-set-associative, 256-kbyte integrated L2 cache, a 32-bit, 66-MHz PCI-bus controller and a PC-100 SDRAM controller with ECC, eliminating the need for an external "Northbridge" chip. It is packaged in a low-cost, 370-pin ceramic PGA.
UltraSPARC IIe at Sun
UltraSPARC IIe SME 1701, 500 MHz
Sun Microsystems UltraSPARC III
The UltraSPARC III, initially shipped in 2001, is the third generation from the UltraSPARC family. It features Scalable Shared Memory (SSM) and is able to scale to up to 1000 processors in a single system.
It was one of the most complex processors available then, comprising 29 million transistors and features such as an embedded memory controller and 9.6 GB-per-second address bus for massive scalability, support for a large 8 MB ECC-protected external cache for minimal latency and a new error isolation and correction "Uptime Bus" (a bus that runs independent of the main system bus, allowing the CPU to be powered-on, configured and tested without requiring that the majority of the system be operational) for high system reliability.
The UltraSPARC III was Sun's first move to boost its aging chip architecture after almost five years. The chip was due 18 months before its introduction, but was delayed for reasons never explained.
The initial version of UltraSPARC III was fabricated by Texas Instruments in a 0.18 µ process technology with aluminum (Al) metal layers. Implemented in this technology, UltraSPARC III operates at frequencies of 600 MHz and 750 MHz. In 2001, UltraSPARC III was upgraded to take advantage of a new TI process technology featuring 0.15 µ features with Copper (Cu) metal layers. Implemented in this more advanced generation of technology, UltraSPARC III operates at frequencies of 900 and 1050 MHz. In 2002, UltraSPARC III Cu was upgraded again to TI’s latest 0.13 µ generation of technology, reaching a top operating frequency of 1200 MHz.
UltraSPARC III announcement
UltraSPARC III at Sun
UltraSPARC III SME 1052A
UltraSPARC III SME 1052B, 900 MHz
Fujitsu / HAL SPARC64
The Fujitsu/HAL SPARC64-III or SPARC64-GP is a SPARC processor conforming to the 64-bit SPARC V9 architecture. When it was released in 1998 it delivered better overall performance than Sun's competing UltraSPARC II at comparable and even lower clock speeds. It has an out-of-order execution engine that can process 63 instructions at once, more than twice the number of instructions possible with the UltraSPARC processor's in-order core. It also has two floating point and two load-store units, delivering twice as many floating point results per cycle as UltraSPARC II. In addition, its instruction and data caches are four times larger and use a four-way set-associative organization, incurring lower miss rates than the caches in UltraSPARC II. Furthermore, the SPARC64-III uses separate buses for the L2 cache and system interfaces, providing greater sustainable memory bandwidth than the UltraSPARC II at comparable clock speeds. In addition, the SPARC64-III uses ECC or parity in TLB and cache arrays, making them more reliable and suitable in mission critical applications than the UltraSPARC II chips, which do not.
SPARC64-III User's Guide
SPARC64-III Microprocessor Report
Fujitsu SPARC64-III/GP MBCS70301HE (HAL)
Fujitsu SPARC64-GP SFCB81147C 450 MHz
Fujitsu SPARC64-GP SFCB81147FP 560 MHz
|April 2006 updates and changes
10 additions to the collection today:
Rare and uncommon processors
The Nx586 is a 586 CPU with a RISC core and translates x86 instructions into efficient RISC code before execution. This processor also features an extra bus for L2 cache running at core speed - other 586 CPUs at that time accessed their L2 cache at external bus speed. It therefore does not run in common Socket 5 or 7 Pentium-boards but requires a special board design.
In later Nx586s, a math coprocessor was included on-chip. Using IBM's multichip module (MCM) technology, NexGen combined the Nx586 and Nx587 FPU die in a single package. The new device, which used the same pinout as its predecessor, was marketed as the Nx586-PF100 to distinguish it from the FPU-less Nx586-P100.
NexGen Nx586 at BYTE
Nx586 Product Brief (AMD)
NexGen: "Clean" Processor
AMD Am5x86-P75+ X5-150ADW
Introduced in November 1995, the AMD 5x86 is a standard 486 processor with an internally-set multiplier of 4, allowing it to run at 133 MHz on systems without official support for clock-multiplied DX2 or DX4 486 processors. Like most of the later 486 parts, the 5x86 featured write-back L1 cache, and unlike all but a few, a generous 16 kilobytes rather than the more common 8KB.
Since having a clock multiplier of four was not part of the original Socket 3 design, AMD made the 5x86 look for a two times setting from the motherboard and interpret that as four times instead. In other words, to use the 5x86 you want to set the motherboard to the 2x setting. This will actually cause the 5x86 to run at 4x.
This version is a quite rare P75+ and has a different clock multiplier of 3. It was designed for 50 MHz 486 systems and ran at an internal speed of 150 MHz.
Fairchild Clipper C100
The Fairchild Clipper C100 architecture was originally developed at Fairchild Semiconductor in Oct. 1985, and began shipping in 1986. It is implemented in a three
chip module consisting of a microprocessor chip and two cache and memory management (CAMMU) chips, mounted on a small PC board.
The architecture was acquired by Intergraph Corporation in 1987.
Instruction Set and Processor Implementation [pdf]
Memory Architecture, Cache and MMU [pdf]
DEC PDP-11 F-11
The DEC F-11 (code name: the Fonz) was DEC's second microprocessor design, and the first to be architected by DEC personnel. The F-11 was substantially more ambitious than its predecessor, the LSI-11. It implemented the entire PDP-11/34 architecture, including FP11-compatible floating point and KT11-compatibile memory management. It targeted 3x the performance of the LSI-11, at almost the same clock rate. It provided physical address extension out to 22 bit, the first system to do so after the PDP-11/70. It implemented the PDP-11 Commercial Instruction Set as an option; the only other implementation was for the PDP-11/44.
Like the LSI-11, the F-11 was a chip set consisting of three designs, one of which could be replicated: the Control Chip (up to nine supported), the Data chip, and the MMU chip. It was implemented in AMI's 6µ NMOS process and operated at 3.6 Mhz (280ns microcycle).
DEC PDP-11 J-11
The DEC J-11 (code name Jaws, which the design team never used) was DEC's fourth and last PDP-11 microprocessor design, and the first to be done in CMOS. The project was co-developed with Harris Semiconductor, who made circuit design and layout.
The J-11 was intended to put a "capstone" on the PDP-11 family by providing the full functionality and performance of the PDP-11/70 in a microprocessor. Accordingly, the J-11 incorporated most of the architectural ornamentation from the 11/70 - dual register sets, data space, supervisor mode - as well as more modern inventions such as SMP support. Microcode-based floating point was standard, with accelerated floating point available as an option. CIS microcode was also intended to be an option.
The J-11 was a chip set consisting of three designs, one of which could be replicated: the Control chip (up to three supported), the Data chip, and the optional FPA (Floating Point Accelerator) chip. The Control and Data chips were implemented in Harris double-poly 4µ P-well CMOS. The FPA was implemented in DEC's double-metal 3µ NMOS process (ZMOS).
The J-11 was introduced late in 1983 at 3.75 Mhz; subsequent tweaks pushed the performance to 4.5 Mhz. The FPA was introduced in 1984 and was used as the basis for the MicroVAX Floating Point Unit and the V-11 F chip.
The Cyrix 5x86 utilizes efficient fifth-generation (Pentium class) architectural features to significantly improve performance while minimizing transistor count. It achieves this performance using a superpipelined architecture in the integer unit combined with data forwarding, branch prediction, a 16-KByte unified write-back cache, single-cycle instruction decode, and single-cycle execution.
The processor's built-in power-saving features automatically power down the Floating Point Unit (FPU) and other idle internal circuits, while the System Management Mode (SMM) conserves power flowing to system peripherals.
The Cyrix 5x86 processor is an example of Cyrix's strategy to design next-generation processor architectures that leverage existing designs. It is available in a 168-pin PGA or a 208-pin QFP package with standard 486 pinout. Though it's installed in a P24D socket on a 486 motherboard, the motherboard must have a BIOS that will support the 5x86.
The two above versions are rather uncommon, a 100 MHz QFP version on an adaptor PCB to fit into a standard 486 socket and the 120 MHz version of the standard PGA 5x86.
Cyrix 5x86 Processor Brief
Cyrix 5x86 Processor FAQs
Chips and Technologies Super386 J38600DX-33
Chips and Technologies was a manufacturer of chipsets for PC motherboards and computer graphics chips. C&T also designed a 386-compatible microprocessor known as the Super386 using clean room design techniques (the method of copying a design by reverse engineering and then recreating it without infringing any of the copyrights and trade secrets associated with the original design), but this chip never enjoyed as much success as the 386 CPUs produced by Intel, AMD, and Cyrix. Another chip by C&T was the Super Math math coprocessor for 386 systems, introduced in 1992, shortly before C&T stopped all work on their CPU and coprocessor development.
C&T was acquired by Intel in 1997, primarily for its graphics chip business.
Intel RapidCAD CPU Upgrade
The Intel RapidCAD is a specially packaged Intel 486DX (RapidCAD-1) without the internal cache and with a standard 386 pinout and a dummy FPU designed as pin-compatible replacements for an Intel 80386 processor and 80387 FPU. Since the 486DX has a working on-chip FPU, a dummy FPU package (RapidCAD-2) is supplied to go in the Intel 387 FPU socket. It contains a simple PAL (Programmable Array of Logic) whose purpose is to generate the signals normally generated by a 387 coprocessor to provide 287 compatible coprocessor exception handling in 386/387 systems motherboards.
RapidCAD information at CPUShack