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DEC PDP-11

DEC PDP-11 F-11

DEC PDP-11 J-11

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The DEC F-11 PDP Microprocessor

The F-11 (code name: the Fonz) was DEC's second microprocessor design, and the first to be architected by DEC personnel. The F-11 was substantially more ambitious than its predecessor, the LSI-11. It implemented the entire PDP-11/34 architecture, including FP11-compatible floating point and KT11-compatibile memory management. It targeted 3x the performance of the LSI-11, at almost the same clock rate. It provided physical address extension out to 22 bit, the first system to do so after the PDP-11/70. It implemented the PDP-11 Commercial Instruction Set as an option; the only other implementation was for the PDP-11/44.

Like the LSI-11, the F-11 was a chip set consisting of three designs, one of which could be replicated: the Control Chip (up to nine supported), the Data chip, and the MMU chip. It was implemented in AMI's 6 µ NMOS process and operated at 3.6 Mhz (280ns microcycle).

References: DEC Microprocessors

DEC PDP-11 F-11

DEC PDP-11 F-11 Top Side

DEC 303E
23-001C7-AA
8201

570000001A1
DEC 8309

DEC 302H
21-15541-AB
8234

DEC PDP-11 F-11 Back Side

BP01

The DEC F-11 is a multi-chip module consisting of 2 chips:
The Control chip (DC303) implements the microword access and sequencing functions of the F-11 chip set. Its key features are:

ROM/PLA control store (138 x 23 bit PLA terms, 414 ROM terms)
Chip set microsequencing
Interrupt logic
Abort logic
Initial decode PLA

The Data chip (DC302) implements the instruction execution path of the F-11 chip set. The Data chip operates under the control of microwords fetched from the Control chip(s). Its key features are:

Execution data path
PDP-11 architectural general registers (16 bit), three stack pointers
Processor status word (PSW)
Microcode temporary registers (16 bit)
Full function arithmetic/logic unit (16 bit)
Single bit shifter/byte swapper
Condition code logic
External interface sequencer

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Core Frequency:	3.6 MHz
Board Frequency:	3.6 MHz
Data bus (ext.):	22 Bit
Address bus:	16 Bit
Transistors:	29,000
Circuit Size:	6.00 µ
Introduced:	1979
Manufactured:	week 09/1983
Package Type:	Ceramic DIP-40

The DEC J-11 PDP Microprocessor

The J-11 (code name Jaws, which the design team never used) was DEC's fourth and last PDP-11 microprocessor design, and the first to be done in CMOS. The project was co-developed with Harris Semiconductor, who made circuit design and layout.

The J-11 was intended to put a "capstone" on the PDP-11 family by providing the full functionality and performance of the PDP-11/70 in a microprocessor. Accordingly, the J-11 incorporated most of the architectural ornamentation from the 11/70 - dual register sets, data space, supervisor mode - as well as more modern inventions such as SMP support. Microcode-based floating point was standard, with accelerated floating point available as an option. CIS microcode was also intended to be an option.

The J-11 was a chip set consisting of three designs, one of which could be replicated: the Control chip (up to three supported), the Data chip, and the optional FPA (Floating Point Accelerator) chip. The Control and Data chips were implemented in Harris double-poly 4 µ P-well CMOS. The FPA was implemented in DEC's double-metal 3 µ NMOS process (ZMOS).

The J-11 was introduced late in 1983 at 3.75 Mhz; subsequent tweaks pushed the performance to 4.5 Mhz. The FPA was introduced in 1984 and was used as the basis for the MicroVAX Floating Point Unit and the V-11 F chip.

References: DEC Microprocessors

DEC PDP-11 J-11

DEC PDP-11 J-11 Top Side

D4-6901-5
DC335
21-1769-11
8802 1618A-3.5

1418673-00
digital
57-19400-08
8841

D4-6900-5
DC334
21-17677-01
8806 1790A

DEC PDP-11 J-11 Back Side

The J-11 is a multi-chip module consisting of 2 chips, both made by Harris Semiconductor:

The Control Chip (DC335) implements the microword access and sequencing functions of the J-11 chip set. Key features:

ROM/PLA control store (512 x 25 bit PLA terms, 768 ROM terms)
Chip set microsequencer
- Next address logic
- Microsubroutine stack
- Interrupt logic
- Abort logic
- Initial decode PLA (Q logic)
External interface sequencer
Instruction prefetch logic

The Data Chip (DC334) implements the instruction execution and memory management data paths of the J-11 chip set. It shares the responsibility for the external interface and for instruction prefetching with the Control chip. The data chip operates under the control of microwords fetched from the Control chip(s). Its key features are:

Execution unit
- PDP-11 architectural general registers (16 bit): dual register set, three stack pointers
- Processor status word (PSW)
- Microcode temporary registers (32 bit)
- Full function arithmetic/logic unit (32 bit)
- Single bit shifter
- Byte swapper
- Conditional branch logic
Memory management unit
- PDP-11 memory management registers: kernel, supervisor, user; instruction and data spaces
- Address translation logic (22 bit)
- Protection logic
External interface sequencer
Instruction prefetch logic

References: Data sheet

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Core Frequency:	4.5 MHz
Board Frequency:	4.5 MHz
Data bus (ext.):	32 Bit
Address bus:	32 Bit
Transistors:	120,000
Circuit Size:	4.00 µ
Introduced:	1983
Manufactured:	week 41/1988
Package Type:	Ceramic DIP-60

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