This is an engineering sample of the first Celeron version. It was made in February 1998, some weeks before the official introduction of the Celeron on April 15th, 1998.

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A Taiwan relabelled Pentium 300 'Tillamook'. The processor inside this fake package is in fact a Mobile Pentium 266 (tape carrier package), soldered on a PGA PCB. The metal heatspreader and lots of thermal compound seems to make this version run somewhat stable at 300 MHz.

The first Celeron (codenamed Covington) is essentially a 266MHz Pentium II manufactured without any secondary cache at all. Although clocked at 266 or 300MHz (substantially higher than the old Pentium MMX), the cacheless Celerons are a good deal slower than the parts they were designed to replace. Substantial numbers were sold on first release, largely on the strength of the Intel name, but the Celeron quickly achieved a poor reputation both in the trade press and among computer professionals. Many people referred to it unkindly but accurately enough as the Slugeron, Celery or Deceleron. The initial market interest faded rapidly in the face of its poor performance and with sales at a very low level, Intel felt obliged to develop a substantially faster replacement as soon as possible.

The Tape Carrier Package (TCP) format is a way to meet the small outline and high leadcount interconnection needs of high performance microprocessors. The TCP has been designed to offer reduced pitch, thin package profiles and smaller footprint on the printed circuit board. For more information see chapter 12 of the Intel Packaging Databook.

While the MMC-1 module used a PCI interface to connect to the notebook motherboard the MMC-2 (Mobile Module Connector 2) uses an AGP/PCI interface.
The MMC-2 has 10 rows and 400 pins.
On the 266MHz version the L2 cache is not included on the processor die. You see 2 cache RAMs and a controller chip on the backside of the module. The 333MHz version CPU includes the L2 cache.

This is an Engineering Sample of a Pentium III Xeon 500MHz in a Pentium II Xeon cartridge. It was manufactured in October 1998, almost half a year before its official introduction in March 1999.
 
Early versions (Code named Tanner) where built in .25 micron technology and featured a 100MHz front side bus, 512KB to 2MB L2 off-die cache sizes and multiprocessor support for up to 8 CPUs.

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The Mendocino Celerons also introduced new packaging. When the Mendocinos debuted they came in both a Slot 1 and Socket 370 PPGA package. The Slot 1 form had been designed to accommodate the off-chip cache of the Pentium II and had mounting problems with motherboards. Because all Celerons are a single-chip design, however, there was no reason to retain the slot packaging for L2 cache storage, and Intel discontinued the Slot 1 variant: beginning with the 466 MHz part, only the PPGA Socket 370 form was offered. (Third-party manufacturers made motherboard slot-to-socket adaptors (nicknamed Slockets) available for a few dollars, which allowed, for example, a Celeron 500 to be fitted to a Slot 1 motherboard.)

This is an Engineering Sample of a Pentium III Xeon 500MHz in a Pentium II Xeon cartridge. It was manufactured in October 1998, almost half a year before its official introduction in March 1999.
 
Early versions (Code named Tanner) where built in .25 micron technology and featured a 100MHz front side bus, 512KB to 2MB L2 off-die cache sizes and multiprocessor support for up to 8 CPUs.

» other pre-production sample chips