A Read/Write Buffer coprocessor for the MIPS R3000 CPU.
The LR3220 Read-Write Buffer (RWB) is the main interface between the CPU and the remainder of the computer system. It provides the buffering necessary for decoupling the internal address and data buses. It enhances performance of MIPS R3000 based systems by buffering write and read operations. Using the LR3220 RWB, systems can perform memory write operations at the cycle rate of the processor, instead of stalling the processor to write data to memory. On memory read operations, the system uses the RWB to pass the read address to main memory, and latch the read data from memory. The LR3220 RWB generates parity, and then passes the data and parity to the processor. A single LR3220 RWB provides six-deep write buffering and one level of read buffering for 32 bits of address and 32 bits of data. It operates at the system clock rate.
The LR3220 buffers CPU/FPU stores for up to six pending writes. There is no gathering or reordering of writes in the LR3220. The data consistency conflicts between reads of write-buffered locations are automatically resolved by the memory controller. The LR3220 takes advantage of the memory system’s page mode cycles to retire writes within the same page each cycle. This results in a peak write bandwidth of 100 MBytes/second with a 25 MHz system clock.
week 04, 1990: 
The LR3220 Read-Write Buffer (RWB) is the main interface between the CPU and the remainder of the computer system. It provides the buffering necessary for decoupling the internal address and data buses. It enhances performance of MIPS R3000 based systems by buffering write and read operations. Using the LR3220 RWB, systems can perform memory write operations at the cycle rate of the processor, instead of stalling the processor to write data to memory. On memory read operations, the system uses the RWB to pass the read address to main memory, and latch the read data from memory. The LR3220 RWB generates parity, and then passes the data and parity to the processor. A single LR3220 RWB provides six-deep write buffering and one level of read buffering for 32 bits of address and 32 bits of data. It operates at the system clock rate.
The LR3220 buffers CPU/FPU stores for up to six pending writes. There is no gathering or reordering of writes in the LR3220. The data consistency conflicts between reads of write-buffered locations are automatically resolved by the memory controller. The LR3220 takes advantage of the memory system’s page mode cycles to retire writes within the same page each cycle. This results in a peak write bandwidth of 100 MBytes/second with a 25 MHz system clock.