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Sun Microsystems UltraSPARC III
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The Sun UltraSPARC III Processor
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The UltraSPARC III, initially shipped in 2001, is the third generation from the UltraSPARC family. It features Scalable Shared Memory (SSM) and is able to scale to up to 1000 processors in a single system.
It was one of the most complex processors available then, comprising 29 million transistors and features such as an embedded memory controller and 9.6 GB-per-second address bus for massive scalability, support for a large 8 MB ECC-protected external cache for minimal latency and a new error isolation and correction "Uptime Bus" (a bus that runs independent of the main system bus, allowing the CPU to be powered-on, configured and tested without requiring that the majority of the system be operational) for high system reliability.
The UltraSPARC III was Sun's first move to boost its aging chip architecture after almost five years. The chip was due 18 months before its introduction, but was delayed for reasons never explained.
The initial version of UltraSPARC III was fabricated by Texas Instruments in a 0.18 µ process technology with aluminum (Al) metal layers. Implemented in this technology, UltraSPARC III operates at frequencies of 600 MHz and 750 MHz. In 2001, UltraSPARC III was upgraded to take advantage of a new TI process technology featuring 0.15 µ features with Copper (Cu) metal layers. Implemented in this more advanced generation of technology, UltraSPARC III operates at frequencies of 900 and 1050 MHz. In 2002, UltraSPARC III Cu was upgraded again to TI’s latest 0.13 µ generation of technology, reaching a top operating frequency of 1200 MHz.
References:
UltraSPARC III announcement
UltraSPARC III at Sun
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