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The IDT 79R3000 / MIPS R3000 Processor
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The first commercial MIPS CPU model, the R2000, was announced in 1985 as a 32-bit implementation. It was followed by the R3000, the first successful MIPS design in the marketplace with more than 1 million processors made. The R3000 was used in high-end UNIX computers by Siemens and DEC and in the Silicon Graphics SGI Personal IRIS 4D/20 graphic workstations. On this machines 3D sequences for movies like The Abyss, Jurrasic Park or Terminator 2 were rendered.
The R3000 has an interface to handle 3 coprocessors. Each coprocessor has a flag line connected with the CPU that can be tested and a conditional branch executed dependent on its value. Coprocessor instructions can be executed directly from the instruction stream.
Coprocessor 0 (CP0) is incorporated on the CPU chip and supports the virtual memory system and exception handling. It is also referred to as the System Control Coprocessor.
CP1 is reserved for the floating point coprocessor. An FPU is mandatory for most R3000 systems. CP2 is available for specific implementations and is often used to accelerate memory access by connecting it to an R3020 memory buffer or an R3220 read/write buffer chip. Later versions of the R3000 (R3000A) had built in memory buffer circuitry.
Reference:
R3000 at SGIstuff
R3000 information (German)
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The MIPS R3010 FPU
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The R3010 is the FPU for the MIPS R3000 CPU. It provides high-speed floating point capability for systems based on the R3000 CPU. The organization of the FPU architecture is similar to that of the R3000 CPU, and allows for optimization of both integer and floating-point performance.
The R3010 FPU connects seamlessly to the R3000 CPU via the R3000 coprocessor interface CP1, and since both units receive instructions in parallel, floating-point instructions can be initiated at the same single cycle rate as fixed-point instructions.
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The IDT R3020 Memory Buffer
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| Early implementations of R2000/R3000 processors had no write buffer circuit inside to isolate the CPU from memory subsystem. There were companion chips for R2000/R3000 to implement write buffering, connected via the CP2 coprocessor interface of the R3000 CPU. Newer designs of the R3000 (R3000A) have built in memory buffer circuitry. |
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The IDT 79R3500 / MIPS R3500 Processor
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The IDT / MIPS R4400 Processor
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The MIPS R4000 series, released in 1991, extended the MIPS instruction set to a full 64-bit architecture and moved the FPU onto the main die to create a single-chip system.
The design was so important to SGI, at the time MIPS' major customer, that SGI bought the company in 1992.
A number of improved versions soon followed, including the R4400.
The R4x00 processors have been available and used in different versions. PC (as in R4400PC) denotes primary cache only and SC denotes secondary cache.
The MC versions contain special support for cache architectures in multiprocessor systems.
R4400 processors where used in many Silicon Graphics computers, e.g. the Indigo2 workstations,
Onyx supercomputers and
Challenge servers.
References:
MIPS R4400 Product Information
R4400 at SGIstuff
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The IDT R4600 Processor
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The IDT R4700 Processor
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The IDT R5000 Processor
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The R5000, designed by Quantum Effect Devices (QED), replaced the R4600 in 1996. The R5000 FPU had more flexible single precision floating-point scheduling than the R4x00,
and as a result, R5000-based SGI Indys had much better graphics
performance than similarly clocked R4400 Indys with the same graphics hardware. SGI gave the old graphics board a new name (XL8 -> XGE8) when it was combined with R5000
in order to emphasize the improvement.
References:
MIPS R5000 introduction
MIPS R5000: Fast, Affordable 3-D
IDT 79RV5000 Documents
R5000 at SGIstuff
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