The J-11 is a multi-chip module consisting of 2 chips, both made by Harris Semiconductor:
The Control Chip (DC335) implements the microword access and sequencing functions of the J-11 chip set. Key features:
ROM/PLA control store (512 x 25 bit PLA terms, 768 ROM terms)
Chip set microsequencer
Next address logic
Microsubroutine stack
Interrupt logic
Abort logic
Initial decode PLA (Q logic)
External interface sequencer
Instruction prefetch logic
The Data Chip (DC334) implements the instruction execution and memory management data paths of the J-11 chip set. It shares the responsibility for the external interface and for instruction prefetching with the Control chip. The data chip operates under the control of microwords fetched from the Control chip(s). Its key features are:
Execution unit
PDP-11 architectural general registers (16 bit): dual register set, three stack pointers
Processor status word (PSW)
Microcode temporary registers (32 bit)
Full function arithmetic/logic unit (32 bit)
Single bit shifter
Byte swapper
Conditional branch logic
Memory management unit
PDP-11 memory management registers: kernel, supervisor, user; instruction and data spaces
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